Public domain (U.S. patent drawing) ↗
Hoerni's Planar Process Patent
- Year
- 1959
- Creator
- Jean Hoerni
- Company
- Fairchild Semiconductor
- Location
- Palo Alto, California
Description
Jean Hoerni's planar process keeps a layer of silicon oxide on the wafer to protect the transistor junctions. The drawing shown comes from his U.S. Patent 3,025,589, filed on May 1, 1959.
Importance
The oxide layer made transistors more reliable and gave them lower leakage current. It also let engineers make all the parts of an integrated circuit from one side of a wafer, as Robert Noyce proposed in 1959. Fairchild started to sell the 2N1613 planar transistor in April 1960.
Interesting fact
Hoerni wrote the idea in his notebook in December 1957, more than a year before he made a working planar transistor in March 1959.
Sources
- 1959: Invention of the Planar Manufacturing Process ↗Computer History Museum, The Silicon Engine
- US Patent 3,025,589: Method of Manufacturing Semiconductor Devices (J. A. Hoerni) ↗U.S. Patent Office, via Google Patents · 1962-03-20